As is well known in the field of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions. These geometries and sizes are often dependent upon the photolithographic resolution available for the particular manufacturing facility. The goal of photolithography in establishing the horizontal dimensions of the various devices and circuits is to create a pattern which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer. As line widths shrink smaller and smaller in submicron photolithography, the process to print lines and contact holes in photoresist becomes increasingly more difficult.
With circuit advancement to the very-large-scale integration (VLSI) levels, more and more layers are added to the surface of the wafer. These additional layers in turn create more steps on the wafer surface. The resolution of small image sizes in photolithography thus becomes more difficult over the additional steps due to light reflection and the thinning of the photoresists over the steps. Planarization techniques become increasingly more important to offset the effects of a varied topography.
In addition to the geometries and sizes of active components, the chip area also depends on the isolation technology used. Sufficient electrical isolation must be provided between active circuit elements so that leakage current does not cause functional or specification failures. Increasingly more stringent specifications, together with the demand, for example, for smaller memory cells in denser memory arrays, places significant pressure on the isolation technology in memory devices, as well as in other modern integrated circuits.
A well-known and widely-used isolation technique is the local oxidation of silicon, commonly referred to as LOCOS. The LOCOS process was a great technological improvement in reducing the area needed for the isolation regions and decreasing some parasitic capacitances. Thermal silicon dioxide is formed is areas not covered by an oxidation barrier such as areas where active devices are to be formed. The oxidation barrier is generally silicon nitride over a pad or gate oxide. The wafer is typically placed in a wet oxidizing environment, generally in steam at a high temperature such as 1000.degree. C. The portions of the wafer not covered by the oxidation barrier are oxidized. This LOCOS field oxide is generally formed to a sufficient thickness that a conductor placed over the field oxide will not invert the channel underneath, when biased to the maximum circuit voltage.
While LOCOS isolation is widely-used in the industry, it is subject to certain well-known limitations. A first significant limitation of LOCOS is lateral encroachment of the oxide into the active regions, known as "birdbeaking", due to oxidation of silicon under the edges of the nitride or barrier mask. The expected distance of such encroachment must be considered in the layout of the integrated circuit because the active area becomes smaller than the initial dimensions of the nitride layer. The encroachment may by reduced by reducing the field oxide thickness, but at a cost of reduction of the threshold voltage of the parasitic field oxide transistor, and thus reduction of the isolation provided.
Attempts to suppress birdbeaking in LOCOS, such as forming thicker nitride barrier layers, cause stress-related defects in the nearby substrate due to the difference in the thermal coefficients of expansion between the silicon substrate and the silicon nitride layers. Process complexity also increases substantially in attempting to avoid these stress-related defects. To achieve submicron geometries, there can be little or no physical loss of the active areas as occurs with the birdbeaking phenomenon.
To reduce the bird's beak effect, there has been proposed the use of a polysilicon layer between the nitride layer and the pad oxide layer as more fully described in U.S. Pat. No. 4,407,696, issued Oct. 4, 1983 to Han et al. The use of the polysilicon layer in the LOCOS process, known as poly-buffered LOCOS or PBLOCOS, is used to reduce oxidation induced stacking faults resulting from the stress caused by the different thermal coefficients of expansion between the silicon substrate and a thick silicon nitride layer overlying the substrate. As described more fully in the publication "Twin-White-Ribbon Effect and Pit Formation Mechanism in PBLOCOS", J. Electrochem. Soc., Vol. 138, No. 7, July 1991 by Tin-hwang Lin et al, the polysilicon layer absorbs the excessive stress caused by the silicon nitride and prevents the lateral encroachment of oxidants, thus reducing the bird's beak.
In addition to the lateral encroachment limitation of LOCOS, the isolation technique of LOCOS adds topography to the integrated circuit surface. The additional topography is a result of the silicon dioxide necessarily occupying a greater volume than that of the silicon prior to its oxidation, due to the reaction of the silicon to oxygen. As a result, the surface of conventional LOCOS field oxide is above the surface of the active regions, with approximately half of the oxide thickness being above the active region surface. This topography requires overlying conductors to cover steps at the edges of the field oxide which presents the potential for problems in patterning and etching the conductor layer and in the reliability of the conductor layer. In addition, the depth of focus required for submicron photolithography can be effectively reduced by the topography of the wafer surface.
In addition to the above described limitations, with the LOCOS or PBLOCOS techniques, an undesired nitride spot forms along the interface of the silicon substrate and silicon oxide regions. These nitride spots are the result of the well-known "Kooi" effect which refers to the formation of a thin layer of silicon nitride along the surface of the silicon substrate as more fully described in U.S. Pat. No. 5,258,333, issued on Nov. 2, 1993 to Shappir et al. This silicon nitride is formed from the reaction of H.sub.2 O and the nitride layer used as the oxidation barrier over the active areas during the step of thermally growing the field oxide. This reaction forms NH.sub.3 which diffuses through the pad or gate oxide to react with the surface of the silicon substrate to form the nitride spots or "white ribbon". These nitride spots or white ribbons limit the growth of subsequently formed oxide layers at these nitride locations. The white ribbons can thus cause poor reliability and substandard performance of devices such as gate electrodes which have gate oxide layers in these locations.
Various PBLOCOS techniques may be used to reduce the oxidation induced stacking faults in conjunction with methods of removing the nitride spots. One such method is described more fully in U.S. patent application Ser. No. 07/809,401 filed on Dec. 18, 1991 to Che-Chia Wei et al. Referring to FIG. 1, a portion of a wafer in which an integrated circuit is to be formed according to the prior art, is illustrated having a substrate 10. An oxide layer 12 is thermally grown over the surface of the substrate 10. A polysilicon layer 14 is formed over the oxide layer 12 and a nitride layer 16 is then formed over the polysilicon layer 14. Photoresist 18 is formed over the nitride layer 16 and patterned and etched to expose a portion of the nitride layer 16 in opening 20 as shown in FIG. 2. Layers 14 and 16 are removed to expose a portion of the oxide layer 12 in opening 22. Referring to FIG. 3, photoresist layer 18 is then removed and an oxidation step is performed, resulting in a field oxide region 24 formed above and below the substrate surface. Layers 12, 14 and 16 which were formed as a barrier over the active areas during the oxidation step are then removed.
Referring to FIG. 4, thin nitride spots 26 are formed along the interface between the oxide and the silicon substrate during the thermal oxidation step in which the field oxide region was formed. These nitride spots may negatively impact device performance of subsequently formed devices in this area and may be removed before any subsequent steps are carried out. There are various methods of removing these nitride spots before devices, such as field effect transistors, are formed, such that the integrity of the devices is maintained. As background information, one such method is described in U.S. Pat. No. 4,553,314 issued on Nov. 19, 1985 to Chan et al. A sacrificial oxide layer 28 is formed over the exposed silicon substrate. As can be seen in FIG. 4, the sacrificial oxide layer 28 is thinned over the area of the nitride spots. However, as layer 28 consumes part of the silicon substrate during formation, it also oxidizes the nitride residue from the substrate. Thus, when layer 28 is removed, the nitride residue is also removed.
After the sacrificial oxide layer is removed, the surface of the silicon substrate is then ready for devices to be formed in the active areas adjacent to the field oxide. Referring to FIG. 5, once the nitride spots are removed, a gate oxide layer 30 and polysilicon layer 32 are formed over the surface of the silicon substrate and the field oxide region 24. This gate oxide/polysilicon stack can then be patterned and etched to form a gate electrode 34 and interconnect 36 as shown in FIG. 6.
The additional steps of forming and removing the sacrificial oxide layer 28 to remove the undesired nitride spots, however, add complexity and thus additional manufacturing costs. The increase in processing steps may lower the yield and lower the reliability due to a higher probability of creating defects. An additional step is also created between the field oxide and substrate which increases the topography over the wafer. This additional topography causes additional step coverage problems at later stages and may present problems in etching the polysilicon gate and the interconnect where it crosses over the field oxide.
It is therefore an object of the present invention to provide a method of forming isolation regions or structures and devices in active areas adjacent to the isolation regions having substantially coplanar upper surfaces to minimize subsequent step coverage problems.
It is a further object of the present invention to provide such a method of forming the active devices adjacent to the isolation regions or structures with significantly fewer processing steps which will decrease the manufacturing complexity and produce higher yields and reliability.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.